AHB：advanced high-performance bus；APB： advanced peripherals bus。

static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;

/*

SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------

SYSCLK 由PLL時(shí)鐘，外部高速時(shí)鐘，內(nèi)部高速時(shí)鐘獲得，最大為72MHz

HCLK 由HCLK經(jīng)過AHB預(yù)分頻器得到，最大72MHz，至AHB總線，核心存儲(chǔ)器和DMA

PCLK2 最大72MHz ,至APB2 外設(shè)

PCLK1 最大36MHz，至APB1外設(shè)

*/
/* 使能高速外部晶振*/
RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* 等待外部高速時(shí)鐘穩(wěn)定*/
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));

if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}

if (HSEStatus == (uint32_t)0x01)
{
/* FLASH 存取控制寄存器配置 使能預(yù)取，兩個(gè)等待周期（36MHz --72MHz為2個(gè)等待周期）*/
FLASH->ACR |= FLASH_ACR_PRFTBE;

/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;

/* 先對(duì)HCLK PCLK1 PCLK2初始化

時(shí)鐘配置寄存器 上電初始化初值應(yīng)為為 0 如下配置的結(jié)果是：

8M的高速內(nèi)部時(shí)鐘為系統(tǒng)時(shí)鐘

HCLK = 8M

PCLK2 = 8M

PCLK1 = 4M

*/
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/

/* 如果定義了STM32F10x_CL 則進(jìn)行如下 配置 該宏定義在編譯選項(xiàng)中定義 */
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
/*

PLL2 配置： 時(shí)鐘信號(hào)輸入源為PREDIV1, 8倍頻后5分頻
*/

/*清零相關(guān)控制域*/

RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

/* 配置CFGR2寄存器*/
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}


/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */

/* Enable PLL 使能PLL*/
RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}

/*

Select PLL as system clock source

選擇PLL時(shí)鐘作為系統(tǒng)時(shí)鐘，并等待穩(wěn)定

*/
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}

HSE(25MHZ)->PREDIV2(5分頻)——5MHZ——>PLL2MUL(8倍頻)——40MHZ——>PREDIV1SCR(選擇PLL2)——40MHZ——>PREDIV1(5分頻)——8MHZ——>PLLSCR(PREDIV1輸入)——8MHZ——>PLLMUL(9倍頻)——72MHZ——>SW(選擇PLL)——SYSCLK(72MHZ).