Sub module name

quantity

Description

Packing FIFO

1

Receive and store processed packets before being packed in “packing center”

Packing center

1

Packing payload with all sorts of heads

Signal name

Bit width

I/O

Description

Data_router_packingfifo

73

input

Input data bus from “payload router”. Bit 64 is set to “0” to indicate this is an uncoded packet

Wr_en_router_packingfifo

1

Input

Write enable

Rdy_router_packingfifo

1

Output

1=module “packing FIFO” is ready to receive from payload router, 0=otherwise

Router_status

3

input

Input FSM state signal to coordinate with the control of “packing FIFO”

Empty_packingfifo

1

output

1=FIFO packing is empty,0=otherwise

Data_converter_packingfifo

73

input

Input data bus from “m72to64 converter”. Bit 64 is set to “1” to indicate this is a coded packet

Wr_en_converter_packingfifo

1

Input

Write enable

Rdy_converter_packingfifo

1

Output

1=module “packing FIFO” is ready to receive from m72to64 converter, 0=otherwise

Empty_converterfifo

1

Input

1=FIFO converter is empty,0=otherwise

Data_center_legacyfifo_1

64

Input

Input data bus from “FIFO ctrl legacy 1”

Rd_en_center_legacyfifo_1

1

output

Read enable

Data_center_packinginfo_1

14

Input

Input data bus from “FIFO ctrl packinginfo 1”

Rd_en_center_packinginfo_1

1

output

Read enable

Data_center_legacyfifo_2

64

Input

Input data bus from “FIFO ctrl legacy 2”

Rd_en_center_legacyfifo_2

1

output

Read enable

Data_center_packinginfo_2

14

Input

Input data bus from “FIFO ctrl packinginfo 2”

Rd_en_center_packinginfo_2

1

output

Read enable

Rand_num_center_1

8

input

Input random number from “m64×64 multiplier 1”

Rand_num_center_2

8

input

Input random number from “m64×64 multiplier 2”

Out_data_out_0

64

output

Output data bus to “output arbiter”

Out_ctrl_out_0

8

Output

Output ctrl bus to “output arbiter”

Data_val_out_0

1

Output

1=data from packing center to output arbiter is valid, 0=otherwise

Rdy_out_0

1

Input

1=output arbiter is ready to receive from packing center, 0=otherwise

clk

1

Input

System clock running at 125 MHz

Rst_n

1

input

System asynchronous reset signal

Signal name

Bit width

Input or output

Description

Out_data_out_0

64

input

input data bus from “packing center”

Out_ctrl_out_0

8

Input

input ctrl bus from “packing center”

Data_val_out_0

1

Input

1=data from packing center to output arbiter is valid, 0=otherwise

Rdy_out_0

1

output

1=output arbiter is ready to receive from packing center, 0=otherwise

Out_data_out_1

64

input

input data bus from “input arbiter 1”

Out_ctrl_out_1

8

Input

input ctrl bus from “input arbiter 1”

Data_val_out_1

1

Input

1=data from input arbiter 1 to output arbiter is valid, 0=otherwise

Rdy_out_1

1

output

1=output arbiter is ready to receive from input arbiter 1, 0=otherwise

Out_data_out_2

64

input

input data bus from “input arbiter 2”

Out_ctrl_out_2

8

Input

input ctrl bus from “input arbiter 2”

Data_val_out_2

1

Input

1=data from input arbiter 2 to output arbiter is valid, 0=otherwise

Rdy_out_2

1

output

1=output arbiter is ready to receive from input arbiter 2, 0=otherwise

Out_data_mac

64

output

output data bus to “MAC Layer”

Out_ctrl_mac

8

Output

output ctrl bus to “MAC Layer”

Data_val_mac

1

Output

1=data from output arbiter to MAC layer is valid, 0=otherwise

Rdy_mac

1

Input

1=MAC layer is ready to receive from output arbiter, 0=otherwise

clk

1

Input

System clock running at 125MHz

Rst_n

1

input

System asynchronous reset signal

信號名稱

位寬 bits

I/O

描述

in_data_n(n:0、1、2、3)

64

input

從MAC層輸入的data數(shù)據(jù)

in_ctrl_n(n:0、1、2、3)

8

input

從MAC層輸入的ctrlbus數(shù)據(jù)

in_wr_n(n:0、1、2、3)

1

input

從MAC層輸入的數(shù)據(jù)寫使能信號（1為有效）

in_rdy_n(n:0、1、2、3)

1

output

輸出至MAC層的準(zhǔn)備信號（1為準(zhǔn)備完畢，可以寫入）

out_data

64

output

輸出至forward模塊的data數(shù)據(jù)

out_ctrl

8

output

輸出至froward模塊的ctrl數(shù)據(jù)

out_wr

1

output

輸出至forward模塊的寫使能信號（1為寫使能有效）

out_rdy

1

input

從forward模塊輸入的準(zhǔn)備信號（1為準(zhǔn)備好，可以寫入）

信號名稱

位寬 bits

I/O

描述

out_data

64

input

從input_arbiter模塊輸出的data數(shù)據(jù)

out_ctrl

8

input

從input_arbiter模塊輸出的ctrl數(shù)據(jù)

out_wr

1

input

從input_arbiter模塊輸出的寫使能信號（1為寫使能有效）

out_rdy

1

input

輸出至input_arbiter模塊的準(zhǔn)備使能信號（1為準(zhǔn)備使能有效）

out_data_n(n:0、1、2、3)

64

output

輸出至MAC層的data數(shù)據(jù)

out_ctrl_n(n:0、1、2、3)

8

output

輸出至MAC層的ctrlbus數(shù)據(jù)

out_wr_n(n:0、1、2、3)

1

output

輸出至MAC層的數(shù)據(jù)寫使能信號（1為有效）

out_rdy_n(n:0、1、2、3)

1

intput

從MAC層輸入的準(zhǔn)備信號（1為準(zhǔn)備完畢，可以寫入）